15. 1. 2020 18:00 - 19:00 SEČ online webinář
This webinar will show the powerful combination of Xpedition Layout routing and HyperLynx SI DDRx Wizard batch simulation to produce optimal DDR4 memory routing in your design. The basic steps will include routing the DDR circuit and simulating the layout in HyperLynx SI. The process includes providing details to Electrical Engineer and ECAD Designer so DDR will be “Correct by Construction” on the very first fabrication. Simulation allows you to find things that could be problems in a complicated layout. Learn how to set up rules so you have a proper set of routing constraints in Xpedition Layout for the DDR Circuit that will work 100% of the time in HyperLynx SI.
Learn Design Methodologies in the Constraint Manager that will save valuable time and can help speed up your design process.
What You Will Learn:
- How to use HyperLynx SI to help develop Xpedition Layout Constraints
- Understanding what happens when HyperLynx SI Runs a DDR batch Simulation
- “Correct by Construction” Strategies for first fabrication results
- HyperLynx SI verification of quality Layout before fabrication
Na tento online seminář se můžete registrovat také přímo ze stránek Mentor.