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Effect of Package Delays on DDRx Timing

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CADware s.r.o. » Aktuálně » Výstavy a semináře » Effect of Package Delays on DDRx Timing

14. 2. 2019 18:00 - 18:30 SEČ online webinář

In this webinar you will learn about how component packages affect signal timing. We will show you how the component package model can be implemented in simualtion to analyze the signal integrity and timing effect. You will also see new features in HyperLynx SI to simplify the modeling and analysis of the package.

What You Will Learn:

  • Package model wrapper utility
  • IBIS Interconnect Model feature (BIRD 189) support
  • How to match net lengths including the package length
  • New package coupling control with the new IBIS syntax

Na tento online seminář se můžete registrovat také ze stránek společnosti Mentor.

Více o programu HyperLynx