Introduction to Visualizer for the VHDL Users

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Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions and Coverage.

This session will introduce the Visualizer Debug Environment for VHDL and UVM.

What You Will Learn:

  • Post-simulation and live-simulation debug
  • Driver tracing and X-tracing
  • Source code debug
  • Waveform debug
  • UVM Debug, including classes and transactions in the waveform

Na tento online seminář se můžete registrovat také ze stránek výrobce programu, společnosti Mentor, A Siemens business.

Více o programu ModelSim